A DPLL is used to create an output signal synchronized in both phase and frequency to a reference signal. A PLL loop including a software-implemented digital controlled oscillator (SDCO) may be used to generate phase and frequency control values for a hardware-implemented controlled oscillator that generates the output clock signal. The PLL loop comprises a phase sampler that samples the phase of reference signals. The SDCO computes the phase and frequency of output clock signal locked to the input reference signal for each cycle of a system clock running the DPLL. An SDCO is used in a software implementation of a Digital Controlled Oscillator (DCO), which offers advantages in terms of flexibility, accuracy, stability and reliability. The SDCO is basically a numerical DCO with selectable precision. Since an SDCO is not limited by hardware, it has an arbitrary precision determined by the software.
The phase and frequency values output by the SDCO must be turned into actual clock signals. This operation is achieved by a hardware-implemented controlled oscillator.
A typical prior art DPLL is shown in FIG. 1. This includes a PLL loop 17 comprising a phase sampler 10 receiving reference input signal ref a phase comparator 12 in the form of a subtractor (an adder with a minus input), a loop filter 14, an SDCO 16, and a converter 18. The converter 18 is coupled to a hardware-implemented oscillator 20, which synthesizes the output clock signals. The hardware-implemented controlled oscillator 20 may be a digital controlled oscillator (DCO) or a voltage controlled oscillator (VCO). In the event that a DCO is utilized, an APLL is normally provided to control an ultimate VCO responsive to the DCO. The DCO/VCO 20 will typically be mounted on a separate die to generate clock signals for an active circuit so as to reduce output clock noise by isolation the SPLL from the real clock output.
The phase sampler 10 generates a digital phase value representing the current phase of the reference signal ref. This is compared in comparator 12 with the phase value output by the SDCO 16 to generate a phase error value. This is passed through the loop filter 14 to generate a control value for the SDCO 16. The control value is in the form of a frequency offset df, which is applied for the amount of time necessary to bring the output of the SDCO back into phase with the reference signal. The loop filter for a type II PLL is shown in more detail in FIG. 5 and as is known in the art comprises a proportional path and an integral path including an integrator. The proportional path includes multiplier 60, which multiplies the phase error value by a parameter Cp (the p parameter) to define the desired filter bandwidth. The integral path includes a multiplier 62, which multiplies the output of multiplier 60 by an integral parameter Ci (the i-parameter), and an adder 64 with a feedback loop including a unit delay module 66 to provide an integrator. An output adder 68 adds the outputs of adder 60 and 62 to produce the frequency offset df.
The SDCO 18 generates phase and frequency values that are passed to converter 18, which converts them to a suitable form for controlling the phase and frequency inputs of the hardware-implemented DCO/VCO 20. The converter 18 takes into account the fact that SDCO16 is a software device and DCO 20 is a hardware device. For example, the SDCO 16 and DCO 20 may have different center frequencies or different bit widths. Normally, SDCO 16 is a numerical DCO and has much higher resolution than hardware DCO 20. The converter 18 is thus a map, typically a linear map, from one frequency to another one with different resolutions, or bit widths.
Since the SDCO 16 is locked to the sampled reference phase value, and the SDCO 16 controls the output of the DCO/VCO 20, the output clock signal is synchronized with the input reference signal. However, it will be appreciated that the fact that the output clock is synchronized in frequency and phase with the reference clock does not necessary mean that it is in alignment with the reference clock as there may be a constant phase difference between the two clocks.
In many applications, it is required that not only is the output clock locked in frequency and phase with the reference, but also that its phase be aligned in time with the reference clock. In a DPLL, the phase alignment of the DCO/VCO 20 output clock can in theory be achieved ensuring that the SDCO 16 and DCO/VCO 20 both run on the same system clock and then directly controlling the output phase of the DCO/VCO 20 with the output phase value generated by the SDCO 16. However, if there is any hardware delay between the SDCO 16 and the DCO/VCO 20 or at the DCO/VCO 20 output pads, this may cause loss of alignment to occur. Moreover, any variation in temperature, environment or output frequency can cause the hardware delay to vary.